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Silicon Labs /MGM240PB32VNN /MVP_S /INSTR4CFG0

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Interpret as INSTR4CFG0

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MVP_S/INSTR4CFG0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ALUIN0REGID 0 (ALUIN0REALZERO)ALUIN0REALZERO 0 (ALUIN0REALNEGATE)ALUIN0REALNEGATE 0 (ALUIN0IMAGZERO)ALUIN0IMAGZERO 0 (ALUIN0IMAGNEGATE)ALUIN0IMAGNEGATE 0ALUIN1REGID 0 (ALUIN1REALZERO)ALUIN1REALZERO 0 (ALUIN1REALNEGATE)ALUIN1REALNEGATE 0 (ALUIN1IMAGZERO)ALUIN1IMAGZERO 0 (ALUIN1IMAGNEGATE)ALUIN1IMAGNEGATE 0ALUIN2REGID 0 (ALUIN2REALZERO)ALUIN2REALZERO 0 (ALUIN2REALNEGATE)ALUIN2REALNEGATE 0 (ALUIN2IMAGZERO)ALUIN2IMAGZERO 0 (ALUIN2IMAGNEGATE)ALUIN2IMAGNEGATE 0ALUOUTREGID

Description

Instruction N Word 0

Fields

ALUIN0REGID

Register ID
ALUIN0REALZERO

Real Zero
ALUIN0REALNEGATE

Real Negate
ALUIN0IMAGZERO

Imaginary Not Zero
ALUIN0IMAGNEGATE

Imaginary Negate
ALUIN1REGID

Register ID
ALUIN1REALZERO

Real Zero
ALUIN1REALNEGATE

Real Negate
ALUIN1IMAGZERO

Imaginary Not Zero
ALUIN1IMAGNEGATE

Imaginary Negate
ALUIN2REGID

Register ID
ALUIN2REALZERO

Real Zero
ALUIN2REALNEGATE

Real Negate
ALUIN2IMAGZERO

Imaginary Not Zero
ALUIN2IMAGNEGATE

Imaginary Negate
ALUOUTREGID

Register ID

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data